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2013 Wu’s Characteristic Set Method for SystemVerilog Assertions Verification
Xinyan Gao, Ning Zhou, Jinzhao Wu, Dakui Li
J. Appl. Math. 2013(SI10): 1-14 (2013). DOI: 10.1155/2013/740194

Abstract

We propose a verification solution based on characteristic set of Wu’s method towards SystemVerilog assertion checking over digital circuit systems. We define a suitable subset of SVAs so that an efficient polynomial modeling mechanism for both circuit descriptions and assertions can be applied. We present an algorithm framework based on the algebraic representations using characteristic set of polynomial system. This symbolic algebraic approach is a useful supplement to the existent verification methods based on simulation.

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Xinyan Gao. Ning Zhou. Jinzhao Wu. Dakui Li. "Wu’s Characteristic Set Method for SystemVerilog Assertions Verification." J. Appl. Math. 2013 (SI10) 1 - 14, 2013. https://doi.org/10.1155/2013/740194

Information

Published: 2013
First available in Project Euclid: 9 May 2014

zbMATH: 1271.94040
Digital Object Identifier: 10.1155/2013/740194

Rights: Copyright © 2013 Hindawi

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Vol.2013 • No. SI10 • 2013
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