Journal of Symbolic Logic

Lower Bounds for Resolution and Cutting Plane Proofs and Monotone Computations

Pavel Pudlak

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Abstract

We prove an exponential lower bound on the length of cutting plane proofs. The proof uses an extension of a lower bound for monotone circuits to circuits which compute with real numbers and use nondecreasing functions as gates. The latter result is of independent interest, since, in particular, it implies an exponential lower bound for some arithmetic circuits.

Article information

Source
J. Symbolic Logic, Volume 62, Issue 3 (1997), 981-998.

Dates
First available in Project Euclid: 6 July 2007

Permanent link to this document
https://projecteuclid.org/euclid.jsl/1183745308

Mathematical Reviews number (MathSciNet)
MR1472134

Zentralblatt MATH identifier
0945.03086

JSTOR
links.jstor.org

Citation

Pudlak, Pavel. Lower Bounds for Resolution and Cutting Plane Proofs and Monotone Computations. J. Symbolic Logic 62 (1997), no. 3, 981--998. https://projecteuclid.org/euclid.jsl/1183745308


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