Bayesian Analysis
- Bayesian Anal.
- Volume 11, Number 1 (2016), 215-245.
Exploiting Multi-Core Architectures for Reduced-Variance Estimation with Intractable Likelihoods
Nial Friel, Antonietta Mira, and Chris J. Oates
Full-text: Open access
Abstract
Many popular statistical models for complex phenomena are intractable, in the sense that the likelihood function cannot easily be evaluated. Bayesian estimation in this setting remains challenging, with a lack of computational methodology to fully exploit modern processing capabilities. In this paper we introduce novel control variates for intractable likelihoods that can dramatically reduce the Monte Carlo variance of Bayesian estimators. We prove that our control variates are well-defined and provide a positive variance reduction. Furthermore, we show how to optimise these control variates for variance reduction. The methodology is highly parallel and offers a route to exploit multi-core processing architectures that complements recent research in this direction. Indeed, our work shows that it may not be necessary to parallelise the sampling process itself in order to harness the potential of massively multi-core architectures. Simulation results presented on the Ising model, exponential random graph models and non-linear stochastic differential equation models support our theoretical findings.
Article information
Source
Bayesian Anal. Volume 11, Number 1 (2016), 215-245.
Dates
First available in Project Euclid: 8 April 2015
Permanent link to this document
https://projecteuclid.org/euclid.ba/1428516724
Digital Object Identifier
doi:10.1214/15-BA948
Mathematical Reviews number (MathSciNet)
MR3447097
Keywords
control variates MCMC parallel computing zero variance
Citation
Friel, Nial; Mira, Antonietta; Oates, Chris J. Exploiting Multi-Core Architectures for Reduced-Variance Estimation with Intractable Likelihoods. Bayesian Anal. 11 (2016), no. 1, 215--245. doi:10.1214/15-BA948. https://projecteuclid.org/euclid.ba/1428516724.
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